jfet switching transistors nchannel maximum ratings rating symbol value unit drainsource voltage v ds 30 vdc draingate voltage v dg 30 vdc gatesource voltage v gs 30 vdc forward gate current i g(f) 50 madc thermal characteristics characteristic symbol max unit total device dissipation fr5 board (1) t a = 25 c derate above 25 c p d 225 1.8 mw mw/ c thermal resistance, junction to ambient r ja 556 c/w junction and storage temperature t j , t stg 55 to +150 c device marking mmbf4391lt1 = 6j; mmbf4392lt1 = 6k; mmbf4393lt1 = 6g electrical characteristics (t a = 25 c unless otherwise noted) characteristic symbol min max unit off characteristics gatesource breakdown voltage (i g = 1.0 m adc, v ds = 0) v (br)gss 30 e vdc gate reverse current (v gs = 15 vdc, v ds = 0, t a = 25 c) (v gs = 15 vdc, v ds = 0, t a = 100 c) i gss e e 1.0 0.20 nadc m adc gatesource cutoff voltage (v ds = 15 vdc, i d = 10 nadc) mmbf4391lt1 mmbf4392lt1 mmbf4393lt1 v gs(off) 4.0 2.0 0.5 10 5.0 3.0 vdc offstate drain current (v ds = 15 vdc, v gs = 12 vdc) (v ds = 15 vdc, v gs = 12 vdc, t a = 100 c) i d(off) e e 1.0 1.0 nadc m adc 1. fr5 = 1.0 0.75 0.062 in. on semiconductor ? semiconductor components industries, llc, 2001 novmeber, 2001 rev. 2 1 publication order number: mmbf4391lt1/d mmbf4391lt1 mmbf4392lt1 mmbf4393lt1 1 2 3 case 31808, style 10 sot23 (to236ab) 2 source 3 gate 1 drain
mmbf4391lt1 mmbf4392lt1 mmbf4393lt1 http://onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) (continued) characteristic symbol min max unit on characteristics zerogatevoltage drain current (v ds = 15 vdc, v gs = 0) mmbf4391lt1 mmbf4392lt1 mmbf4393lt1 i dss 50 25 5.0 150 75 30 madc drainsource onvoltage (i d = 12 madc, v gs = 0) mmbf4391lt1 (i d = 6.0 madc, v gs = 0) mmbf4392lt1 (i d = 3.0 madc, v gs = 0) mmbf4393lt1 v ds(on) e e e 0.4 0.4 0.4 vdc static drainsource onresistance (i d = 1.0 madc, v gs = 0) mmbf4391lt1 mmbf4392lt1 mmbf4393lt1 r ds(on) e e e 30 60 100 w smallsignal characteristics input capacitance (v ds = 15 vdc, v gs = 0, f = 1.0 mhz) c iss e 14 pf reverse transfer capacitance (v ds = 0, v gs = 12 vdc, f = 1.0 mhz) c rss e 3.5 pf typical characteristics t j = 25 c i d , drain current (ma) , turn-on delay time (ns) d(on) t 5.0 2.0 20 10 0.5 1.0 3.0 7.0 5.0 1.0 50 100 0.7 2.0 10 20 i d , drain current (ma) , rise time (ns) r t figure 1. turnon delay time figure 2. rise time r k = r d' r k = 0 r k = r d' r k = 0 i d , drain current (ma) , turn-off delay time (ns) d(off) t figure 3. turnoff delay time r k = r d' r k = 0 i d , drain current (ma) figure 4. fall time r k = r d' r k = 0 , fall time (ns) f t mmbf4391 mmbf4392 mmbf4393 30 50 200 500 1000 0.5 1.0 3.0 7.0 5.0 0.7 2.0 10 20 30 50 5.0 2.0 20 10 1.0 50 100 200 500 1000 0.5 1.0 3.0 7.0 5.0 0.7 2.0 10 20 30 50 0.5 1.0 3.0 7.0 5.0 0.7 2.0 10 20 30 50 5.0 2.0 20 10 1.0 50 100 200 500 1000 5.0 2.0 20 10 1.0 50 100 200 500 1000 t j = 25 c mmbf4391 mmbf4392 mmbf4393 t j = 25 c mmbf4391 mmbf4392 mmbf4393 t j = 25 c mmbf4391 mmbf4392 mmbf4393 v gs(off) = 12 v = 7.0 v = 5.0 v v gs(off) = 12 v = 7.0 v = 5.0 v v gs(off) = 12 v = 7.0 v = 5.0 v v gs(off) = 12 v = 7.0 v = 5.0 v
mmbf4391lt1 mmbf4392lt1 mmbf4393lt1 http://onsemi.com 3 figure 5. switching time test circuit figure 6. typical forward transfer admittance figure 7. typical capacitance i d , drain current (ma) 2.0 5.0 3.0 7.0 0.5 1.0 3.0 7.0 5.0 50 30 10 20 0.7 2.0 10 20 , forward transfer admittance (mmhos) fs v 10 2.0 15 3.0 5.0 7.0 0.5 1.0 3.0 30 5.0 0.3 0.1 10 0.05 0.03 v r , reverse voltage (volts) c, capacitance (pf) t channel = 25 c v ds = 15 v t channel = 25 c (c ds is negligible c gs -v dd v gg r gg r t r gen 50 w v gen r k r d output input 50 w 50 w set v ds(off) = -10 v input pulse t r 0.25 ns t f 0.5 ns pulse width = 2.0 m s duty cycle 2.0% r gg > r k r d' = r d (r t + 50) r d + r t + 50 figure 8. effect of gatesource voltage on drainsource resistance 80 120 160 200 50 1.0 3.0 170 5.0 20 -10 -40 2.0 80 140 -70 v gs , gate-source voltage (volts) r 4.0 0 40 100 ma 125 ma 75 ma 50 ma 25 ma i dss = 10 ma t channel = 25 c figure 9. effect of temperature on drainsource onstate resistance 1.8 1.0 2.0 1.2 1.4 1.6 0.8 0.6 0.4 i d = 1.0 ma v gs = 0 , drain-source on-state ds(on) resistance (normalized) t channel , channel temperature ( c) 1.5 1.0 c gd 110 6.0 7.0 8.0 0 r , drain-source on-state ds(on) resistance (ohms) mmbf4393 mmbf4392 mmbf4391 note 1 the switching characteristics shown above were measured using a test circuit similar to figure 5. at the beginning of the switching interval, the gate voltage is at gate supply voltage (v gg ). the drainsource voltage (v ds ) is slightly lower than drain supply voltage (v dd ) due to the voltage divider. thus reverse transfer capacitance (c rss ) of gatedrain capacitance (c gd ) is charged to v gg + v ds . during the turnon interval, gatesource capacitance (c gs ) dis- charges through the series combination of r gen and r k . c gd must discharge to v ds(on) through r g and r k in series with the parallel combination of effective load impedance (r' d ) and drainsource resistance (r ds ). during the turnoff, this charge flow is reversed. predicting turnon time is somewhat difficult as the channel re- sistance r ds is a function of the gatesource voltage. while c gs dis- charges, v gs approaches zero and r ds decreases. since c gd dis- charges through r ds , turnon time is nonlinear. during turnoff, the situation is reversed with r ds increasing as c gd charges. the above switching curves show two impedance conditions; 1) r k is equal to r d' which simulates the switching behavior of cascaded stages where the driving source impedance is normally the load impedance of the previous stage, and 2) r k = 0 (low im- pedance) the driving source impedance is that of the generator.
mmbf4391lt1 mmbf4392lt1 mmbf4393lt1 http://onsemi.com 4 figure 10. effect of i dss on drainsource resistance and gatesource voltage i dss , zero-gate voltage drain current (ma) , drain-source on-state ds(on) r 20 10 30 40 50 30 40 50 60 70 20 resistance (ohms) 0 10 0 1.0 2.0 3.0 4.0 5.0 , gate-source voltage gs v (volts) t channel = 25 c v gs(off) r ds(on) @ v gs = 0 6.0 7.0 8.0 9.0 10 70 60 80 90 100 80 90 100 110 120 130 140 150 note 2 the zerogatevoltage drain current (i dss ) is the principle determinant of other jfet characteristics. figure 10 shows the relationship of gatesource off voltage (v gs(off) ) and drainsource on resistance (r ds(on) ) to i dss . most of the de- vices will be within 10% of the values shown in figure 10. this data will be useful in predicting the characteristic varia- tions for a given part number. for example: unknown r ds(on) and v gs range for an mmbf4392 the electrical characteristics table indicates that an mmbf4392 has an i dss range of 25 to 75 ma. figure 10 shows r ds(on) = 52 ohms for i dss = 25 ma and 30 ohms for i dss = 75 ma. the corresponding v gs values are 2.2 volts and 4.8 volts.
mmbf4391lt1 mmbf4392lt1 mmbf4393lt1 http://onsemi.com 5 the values for the equation are found in the maximum ratings table on the data sheet. substituting these values into the equation for an ambient temperature t a of 25 c, one can calculate the power dissipation of the device which in this case is 225 milliwatts. information for using the sot23 surface mount package minimum recommended footprint for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. with the correct pad geometry, the packages will self align when subjected to a solder reflow process. sot23 mm inches 0.037 0.95 0.037 0.95 0.079 2.0 0.035 0.9 0.031 0.8 sot23 power dissipation p d = t j(max) t a r q ja p d = 150 c 25 c 556 c/w = 225 milliwatts the power dissipation of the sot23 is a function of the pad size. this can vary from the minimum pad size for soldering to a pad size given for maximum power dissipa- tion. power dissipation for a surface mount device is deter- mined by t j(max) , the maximum rated junction temperature of the die, r q ja , the thermal resistance from the device junction to ambient, and the operating temperature, t a . using the values provided on the data sheet for the sot23 package, p d can be calculated as follows: the 556 c/w for the sot23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milli- watts. there are other alternatives to achieving higher power dissipation from the sot23 package. another alternative would be to use a ceramic substrate or an aluminum core board such as thermal clad ? . using a board material such as thermal clad, an aluminum core board, the power dissipation can be doubled using the same footprint. soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. there- fore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. ? always preheat the device. ? the delta temperature between the preheat and soldering should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. when using infrared heating with the reflow soldering method, the difference shall be a maximum of 10 c. ? the soldering temperature and time shall not exceed 260 c for more than 10 seconds. ? when shifting from preheating to soldering, the maximum temperature gradient shall be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied during cooling. * soldering a device without preheating can cause exces- sive thermal shock and stress which can result in damage to the device.
mmbf4391lt1 mmbf4392lt1 mmbf4393lt1 http://onsemi.com 6 package dimensions case 31808 issue af sot23 (to236ab) d j k l a c b s h g v 3 1 2 dim a min max min max millimeters 0.1102 0.1197 2.80 3.04 inches b 0.0472 0.0551 1.20 1.40 c 0.0350 0.0440 0.89 1.11 d 0.0150 0.0200 0.37 0.50 g 0.0701 0.0807 1.78 2.04 h 0.0005 0.0040 0.013 0.100 j 0.0034 0.0070 0.085 0.177 k 0.0140 0.0285 0.35 0.69 l 0.0350 0.0401 0.89 1.02 s 0.0830 0.1039 2.10 2.64 v 0.0177 0.0236 0.45 0.60 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. style 10: pin 1. drain 2. source 3. gate
mmbf4391lt1 mmbf4392lt1 mmbf4393lt1 http://onsemi.com 7 notes
mmbf4391lt1 mmbf4392lt1 mmbf4393lt1 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mmbf4391lt1/d thermal clad is a trademark of the bergquist company. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
|
